As the speed and performance of digital systems increase, demands on interconnects that “link” these systems also increase. “Links” are communications paths between systems, sub-systems, and components enabling them to exchange data. Digital data can be transferred as pulses of electrical energy over electrically conductive material such as metal wires. An alternate technique for conveying digital data is by pulses of light over optic fiber.
Traditionally, serial line protocols employing encoded clock and data have been the protocols of choice for long-haul applications such as WAN (Wide Area Network), LAN (Local Area Network), SAN (Storage Area Network), as well as other proprietary links. This dominance includes both wire and fiber optic networks. A trend has also emerged at bandwidths of 2.5 Gb/s (current base line) and 10 Gb/s (projected to arrive within a few years) with companies that manufacture servers and routers as well as other high-speed digital systems vendors having begun to adopt serial line protocols as their high-speed backplane interconnect to implement their systems. This approach is being adopted for raising the overall throughput of digital systems.
The physical implementation of serial protocols of encoded clock and data is based on PLL (Phase Locked Loop) architectures to first recover the encoded clock and then employ the clock to sample received data. Critical design factors for a typical PLL are the LPF (Low Pass Filter) and VCO (Voltage Controlled Oscillator) that are area intensive for their implementation and guard-band or “keep-out” region.
The overall bandwidth of a serial link is determined by the characteristics of the interconnect medium and the PLL's ability to accurately recover the encoded clock. Hence, the bandwidth of a serial link cannot be increased easily from the original implementation, requiring a significant re-architecting and design effort.
Alternatively, parallel line protocols utilize like wires or optic fibers that simultaneously transfer a number of bits of digital data equal to the number of wires or optic fiber channels used, called “words.” Ideally, all bits pertaining to a particular word arrive at the intended destination simultaneously and are sampled on the occurrence of the next available clock edge. In practice, however, this is typically not the case for high-speed parallel data links. That is, due to variations in the materials used to construct either wire or optic fiber links, as well as variations in fabrication process, the propagation delay or speed of the digital signals comprising the bits will vary slightly among wires or optic fibers. This results in differences in arrival times of the bits, referred to as “signal skew” or simply “skew.” Wire skew and skew in optic fibers (skew contribution of wire or optic fiber) is proportional to the physical length of the path included in the parallel link. As the amount of skew between the lines of a parallel link increases, the skew further reduces the amount of bit “overlap” observed at the link's destination, thereby increasing the likelihood of a data sampling error. As a result, parallel links without a means of compensating for skew typically tolerate a total (both line and circuit) skew budget of less than 20% of the nominal bit time. This limits the operational distance and bandwidth of most parallel links to less than 10 meters in cable running at approximately 400 Mb/s and 0.15 meters at 1.0 Gb/s using the more common backplane fabrication materials.
Compensation techniques for skew in parallel links are known. One approach to compensate for skew was developed for the ANSI HIPPI-6400-PHY standard by Silicon Graphics, Inc. located in Mountain View, Calif. As disclosed in U.S. Pat. No. 6,031,847, a training sequence is used to measure the amount of skew between each of the parallel channels, that includes clock, data, frame, and control bits. The training sequence is comprised of four sub-sequences: 1) preamble, 2) flush sequence, 3) ping sequence, and 4) post-amble. Assuming that the leading edge of the ping sequence of all channels is aligned at the time of launch from the source, any difference in arrival times at the destination represents the amount of skew present among the channels. Based on measurements, additional delay is added to each channel to re-establish the alignment of the received bits. Once edge alignment has been re-established, the clock signal is further delayed to center its edges with respect to the center of the data bits to more accurately recover received data.
Considered in more detail, FIG. 1 shows a timing diagram of the training sequence developed for the HIPPI-6400 ANSI standard. Shown is the training sequence having four sub-sequences consisting of a preamble command, flush, ping, and post-amble. The training sequence is “balanced” with zero and one assertion times being equal. An important feature is that the length of the flush and ping sequences must match, and the length of each sequence must exceed the total skew for the link to be compensated.
Additionally, FIG. 2 shows a block diagram for a known data channel architecture having a conventional delay line, namely, a SuMAC data channel. The SuMAC DSCC's (Dynamic Skew Compensation Circuit) data channel consists of input measurement control circuitry and logic, an inverter chain, measurement latch, tap decode logic, and tap-select “OR” tree. The length of the inverter chain and all other associated structures must be equal to or larger than the skew to be compensated.
There are three key attributes of this architecture that must be considered when extending the “skew range.” A first attribute to be considered is that the training sequence used in this scheme creates flush and ping sub-sequences during which the switching activity on the parallel link goes to zero for a period of time. This period of switching inactivity introduces a short-term drift in the DC balance of copper cable and ambient light level of fiber optic links. Short-term drift of both DC balance and ambient light produces a “start-up” uncertainty or “jitter” phenomenon when switching activity resumes on the link. The “start-up jitter” phenomenon occurs at the critical flush and ping sub-sequence boundary, thereby affecting the accuracy of the skew measurement. Hence, when the training sequence is modified to accommodate a greater skew range, the flush and ping sub-sequences must be increased, which creates a larger imbalance in the DC level of a copper cable link or ambient light level for a fiber optic link. Ultimately, this can reduce the maximum bandwidth obtainable due to measurement error caused by larger amounts of “start-up jitter” being introduced into the skew measurement.
A second attribute that must be considered is the number of channels that can be practically constructed. As shown in FIG. 2, an internal signal, “All_Present,” generated by the logical “AND” of the individual ping signals received by all of the channels must be re-distributed to all of the channels of the parallel bus in order to capture the skew values. As the number of channels increases, the logical “AND” function must also increase, thereby requiring more time to complete this function. Hence, the overall size of all of the channels delays the arrival time of the “All_Present” signal, requiring the delay line to be lengthened and the overall size of the delay stack to be increased, resulting in higher power dissipation.
A third attribute concerns the overall length of the delay that governs the total amount skew that can be handled. Hence, to increase the skew range, the length of a delay line comprising the hardware and overall size of the delay stack must be increased proportionately. As a result, the delay line is more difficult to design, and the increased size also increases the power that is dissipated.
It would therefore be desirable to effectively correct for skew in a parallel link at higher bandwidths to assure that data is accurately sampled. It would also be desirable to enable skew to be corrected using hardware that does not require a long delay line or increase power consumption. Additionally, it would be desirable to provide a skew correction architecture that is scalable to avoid having to redesign the hardware from one application to another.